I was trying to use IAR + JLink to download and debug SW to 7697. Based on https://docs.labs.mediatek.com/resource/mt7687-mt7697/en/get-started-linkit-7697-hdk/iar-embedded-workbench-linkit-7697/build-and-download-iar-examples-linkit-7697, double checked my wiring.
JLink Base, JTAG 20-pin to 7697 mapping:
JTAG pin 1 VTref <==> 7697 pin 3.3V
JTAG pin 7 TMS <==> 7697 pin 16 SWDIO
JTAG pin 9 TCK <==> 7697 pin 17 SWCLK
JTAG pin 15 RESET <==> 7697 pin RST
JTAG pin GND <==> 7697 pin GND
After config SWD in IAR and triggered downloading, the flashing process failed in "DP error while reading DP-Ctrl-Stat register" or "Failed to get CPU status after 4 retries".
When closely check the error log, I could find CPU reset was not done properly. Need help on this. Thanks.